RSS
当前位置:好得行业软件网下载中心行业软件电子电路Mentor Graphics ModelSim SE 6.3


软件非免费下载,如有需要请联系以上方式获取


软件大小:0 Bytes 下载次数:0
更新时间:2010-07-12 10:37:04
点这里下载 → 此软件暂不提供下载
不能下载请报告错误,谢谢
软件简介:上一页Mentor Graphics FPGA Advantage 7.3 linux 下一页Mentor Graphics Precision Synthesis 2006a.92 linux

Mentor Graphics ModelSim SE 6.3
软件简介—SoftWare Description: Mentor Graphics ModelSim SE 6.3 HDL语言仿真器

::::::English Description::::::

 ModelSim SE (Special Edition) is our UNIX, Linux, and Windows-based simulation and debug environment, combining high performance with the most powerful and intuitive GUI in the industry.

Features
Multi-language, high performance simulation engine
Verilog, VHDL, SystemVerilog Design
Code Coverage
SystemVerilog for Design
Integrated debug
JobSpy Regression Monitor
Mixed HDL simulation option
SystemC Option
TCL/tk
32 and 64-bit platform support -- Solaris, Linux, Windows
Benefits
High performance HDL simulation solution for FPGA & ASIC design teams
The best mixed-language environment and performance in the industry.
Intuitive GUI for efficient interactive or post-simulation debug of RTL and gate-level designs
Merging, ranking and reporting of code coverage for tracking verification progress
Sign-off support for popular ASIC libraries
All ModelSim products are 100% standards based. This means your investment is protected, risk is lowered, reuse is enabled, and productivity is enhanced.
Award-winning technical support.
 


ModelSim专业版,VHDL、Verilog和Mixed-HDL仿真器
Mentor Graphics ModelSim SE 6.3是业界最优秀的HDL语言仿真器,它提供最友好的调试环境,是唯一的单内核支持VHDL和Verilog混合仿真的仿真器。是作FPGA/ASIC设计的RTL级和门级电路仿真的首选,它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术,编译仿真速度快,编译的代码与平台无关,便于保护IP核,个性化的图形界面和用户接口,为用户加快调错提供强有力的手段。全面支持VHDL和Verilog语言的IEEE 标准,支持C/C++功能调用和调试

具有快速的仿真性能和最先进的调试能力,全面支持UNIX(包括64位)、Linux和Windows平台。
主要特点:
RTL和门级优化,本地编译结构,编译仿真速度快;
单内核VHDL和Verilog混合仿真;
源代码模版和助手,项目管理;
集成了性能分析、波形比较、代码覆盖等功能;
数据流ChaseX;
Signal Spy;
C和Tcl/Tk接口,C调试
 

关于本站 | 网站帮助 | 广告合作 | 下载声明 | 友情连接 | 网站地图
客服系统 Copyright © 2003-2008 HaoDeSoft.COM. All Rights Reserved .
haodesoft.com -